DiLinKer MCIO x8 to 2*MCIO x4, SFF-TA-1016 74Pin to 2*SFF-TA-1016 38Pin, PCIe Gen5 Mini Cooledge IO, Double Straight Cable 70cm(CBL-MCIO-1235M5Y)
DiLinKer MCIO x8 to 2*MCIO x4, SFF-TA-1016 74Pin to 2*SFF-TA-1016 38Pin, PCIe Gen5 Mini Cooledge IO, Double Straight Cable 70cm(CBL-MCIO-1235M5Y)
Split one PCIe 5.0 MCIO 8x port into two MCIO 4x ports. The DiLinKer RMC74-6891 (70 cm) takes a single MCIO 8x host connector (SFF-TA-1016, 74-pin) and breaks its eight lanes out to two MCIO 4x connectors (SFF-TA-1016, 38-pin), four lanes each — the cable for feeding 4-lane MCIO devices from a board whose headers are all 8-lane.
Why this cable
- PCIe 5.0 rated, 32 GT/s per lane. Two full x4 links at up to about 15.75 GB/s each; backward compatible with Gen4/Gen3.
- 8 lanes in, 2 × x4 out. A physical lane split — no switch chip, no retimer, no driver.
- Keeps everything on MCIO. For chassis where both the host headers and the device ports are MCIO, no adapter generation-mixing needed.
- Double straight construction. Two separate straight legs for clean routing around risers.
- Passive assembly. No power draw, nothing to configure.
Specifications
| Host connector | MCIO 8x, SFF-TA-1016, 74-pin |
| Device connectors | 2 × MCIO 4x, SFF-TA-1016, 38-pin |
| Lane configuration | 8 host lanes → 2 × 4 device lanes |
| PCIe generation | PCIe 5.0 (32 GT/s per lane); backward compatible with 4.0 / 3.0 |
| Bandwidth per port | Up to 128 GT/s (about 15.75 GB/s at Gen5 x4) |
| Protocol | PCIe only — MCIO carries no SAS or SATA |
| Length | 70 cm / 27.6 in |
| Part number | RMC74-6891 |
| EAN | 6970958106632 |
| Warranty | 24 months |
Compatibility
Works with
- PCIe 5.0 boards with an MCIO 8x (SFF-TA-1016 74-pin) header.
- MCIO 4x (38-pin) inputs on NVMe backplanes, U.2 adapters and drive cages.
- PCIe 4.0 and 3.0 equipment — links negotiate down automatically.
Does not work with
- SAS or SATA devices. MCIO carries PCIe lanes only.
- SlimSAS (SFF-8654) device ports — for those use the MCIO to SlimSAS version.
- OEM systems that re-map the MCIO pinout (some Dell, HPE and Lenovo chassis) — check with us first.
Typical deployments
- Gen5 NVMe tier. Feed two 4-lane MCIO device groups from one host header.
- Board refresh. Keep MCIO 4x backplanes when the new platform standardises on 8x headers.
- Riser-friendly routing. Two straight legs route around risers better than one wide bundle.
Frequently asked questions
Do I need to enable PCIe bifurcation?
If the board wires the MCIO 8x header as a single x8 root port, enable x4x4 bifurcation in the BIOS. Many boards present the header as 2 × x4 or drive it from a PCIe switch, in which case no change is needed. The board manual will say which.
MCIO 8x and 4x — what is the difference?
Connector width and lane count: the 8x is 74-pin carrying eight lanes, the 4x is 38-pin carrying four. They use the same SFF-TA-1016 standard family but will not mate with each other, hence this cable.
Can I run SAS through it?
No. The MCIO host port carries PCIe only, so the device side must be PCIe equipment such as an NVMe backplane.
Is 70 cm fine at Gen5?
At 32 GT/s every centimetre counts. Keep the run direct, avoid sharp folds, and if a link trains below Gen5 check routing first — the hardware will fall back to Gen4 safely.
In the box
- 1 × MCIO 8x to 2 × MCIO 4x cable, 70 cm (RMC74-6891)
Backed by a 24-month warranty. If a link trains at reduced width or does not appear, contact us with your controller and device models and we will help you isolate the cause.
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